1. Field of the Invention
This invention relates to a heterojunction FET (Field Effect Transistor), and more particularly to a heterojunction FET, formed on a GaAs substrate, in which a high gain is obtained in such a high frequency band having a wavelength on the order of millimeter.
2. Related Art
Referring to FIG. 2, a heterojunction FET of a prior-art technique which provides a high gain in a millimeter wavelength band will be explained. This heterojunction FET includes a semi-insulating GaAs substrate 1, an undoped and graded In.sub.(0-0.5) Al.sub.(1-0.5) As layer (buffer layer) 2A having a film thickness of 1000 nm, an undoped In.sub.0.5 Al.sub.0.5 As layer (first barrier layer) 3A having a film thickness of 100 nm, an In.sub.0.5 Ga.sub.0.5 As layer (channel layer) 4A having a film thickness of 15 nm, a silicon-doped N-type In.sub.0.5 Ga.sub.0.5 As layer (second barrier layer) 5A having a film thickness of 50 nm, a silicon-doped N-type In.sub.0.5 Al.sub.0.5 As layer (contact layer) 6A having a film thickness of 100 nm, a gate electrode 7 disposed on the second barrier layer 5A to form a Schottky junction, and a source and drain electrodes 8 and 9, each of which is disposed on the contact layer 6A with an ohmic contact.
In a case where an In.sub.x Ga.sub.1-x As layer is employed as the channel layer 4A which is sandwiched between the In.sub.x Al.sub.1-x As layers 3A and 5A, the difference in band-gaps between the channel layer and the barrier layer is enlarged and the lattice constants in both layers are in good coincidence, particularly if 0&lt;x.ltoreq.0.5, as shown in FIG. 3, where x stands for a compositional ratio of In in an atomic ratio.
The large value of the difference in band-gaps and the coincidence of lattice constants are advantageous in order to confine electrons to the inside of the channel layer 4A. The channel layer 4A is sandwiched between the two barrier layers 3A and 5A to form a quantum well in a conduction band.
With the prior-art example shown in FIG. 2, the compositional ratio of In is of such a large value as 0.5 that in comparison with a case in which the compositional ratio of In is low, the band gap of the channel layer 4A is small, e.g., on the order of about 0.7 eV, and the effective mass of an electron is also small to obtain a high mobility of the electron.
Further, since the potential difference between each of the barrier layers 3A and 5A and the channel layer 4A is large, such as about 0.3 eV, the leakage of electons from the inside of the channel layer 4A to the buffer side is reduced to accomplish a reduction in drain conductance (gd) and an improvement in transconductance (gm). As a result, these arrangements in the heterojunction FET provide higher grain in high-frequency operation.
With the prior-art example, these effects arise from the fact that the compositional ratio of In in the channel layer 4A and barrier layers 3A and 5A is high. However, the lattice constants of these layers differ by about 0.02 nm from that of GaAs, so that dislocation is produced when a layer having a thickness greater than about 5 nm, which is a critical film thickness, is disposed on the semi-insulating GaAs substrate 1 directly.
The occurrence of dislocation and strain are suppressed by lowering a temperature for crystal growth in the buffer layer 2A from normally used 520.degree. C. to 450.degree. C. to produce a slight offset from stoichiometry, gradually increasing the compositional ratio of In up to 0.5 together with the film thickness, while the ratio is set to 0 on one side, and enlarging the film thickness to 1000 nm.
Referring to FIG. 4, which is a sectional view showing a second example of the prior-art, the heterojunction FET includes the semi-insulating GaAs substrate 1, an In.sub.0.2 Ga.sub.0.8 As layer (buffer layer) 2B having a film thickness of 1000 nm, an undoped GaAs layer (first barrier layer) 3B having a film thickness of 50 nm, an In.sub.0.4 Ga.sub.0.6 As layer (channel layer) 4B having a film thickness of 15 nm, a silicon-doped In.sub.0.4 Al.sub.0.8 As layer (second barrier layer) 5B having a film thickness of 50 nm, a silicon-doped In.sub.0.5 Ga.sub.0.6 As layer (contact layer) 6B having a film thickness of 100 nm, the source electrode 8, the drain electrode 9 and the gate electrode 7. Electrical characteristics in line with those of the first example of the prior art can be expected.
With the second prior art example, the first barrier layer 3B is formed of GaAs for the purpose of making the buffer layer unnecessary. However, the thicknesses of the channel layer 4B and second barrier layer 5B cannot be made greater than the critical film thickness.
Accordingly, In.sub.0.2 Ga.sub.0.8 As having a value of 0.2 as an In ratio which is a half that of the channel layer 4B and a lattice constant close to that of GaAs, is inserted as a buffer layer, the film thickness of which is made to be such a large value as 1000 nm, thereby providing relaxation for stress and dislocation, especially when the second barrier layer 5B is disposed on the channel layer 4B with a film thickness larger than the critical film thickness.
If the compositional ratio of In is made less than or equal to 0.2, a heterojunction FET can be formed by disposing an In.sub.x Al.sub.1-x As layer as a barrier layer on the semi-insulating GaAs substrate 1 directly or via a GaAs buffer layer and disposing an In.sub.x Ga.sub.1-x As layer as a channel layer on the barrier layer.
With this arrangement, however, the band gap of the channel layer is too large and a sufficient transconductance gm is not obtained. Further, electrons cannot well be confined in the channel layer. Though the above-described first and second examples of the prior art have been proposed for overcoming these shortcomings, they have not necessarily succeeded.
With the first example of the prior art, the temperature for crystal growth is lowered in an effort to control a shift from stoichiometry. However, the control is essentially difficult and there is a deterioration in crystallization properties. Further, since graded growth requires a large film thickness, dislocation occurs in the course of film growth. As a result, normal crystal growth and transistor operation are not achieved in actuality.
With the second example of the prior art, dislocation is reduced and only minor difficulties are encountered in terms of crystallization. However, since GaAs or In.sub.0.4 Al.sub.0.6 As having a band gap smaller than that of the first example of the prior art is used as a barrier layer, the electrons in the channel layer flow into the barrier layer to generate a leakage current. As a result, the reduction of the drain conductance gd and enhancement of the transconductance gm cannot be realized so that there is no improvement in transistor characteristics. More specifically, it is difficult to realize an FET which is superior to a heterojunction FET with a compositional ratio of In being 0.2.